The International Software & Productivity Engineering Institute (INTSPEI) will partner with the Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems (DTVCS 2008), which will be hosted at the IASTED International Conference on Circuits and Systems (CS 2008) in Kailua-Kona, Hawaii, USA on August 18-20, 2008.

Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems (DTVCS 2008) invites software and hardware engineering researchers, computer scientists and industry luminaries to share theories, new ideas, proven techniques and experiences related to all areas of design, testing and formal verification techniques for integrated circuits and systems.

Topics of interest include, but are not limited to theory and foundations: model checking, SAT-based methods, use of PSL, compositional and probabilistic methods, testing and verification applications and methods, etc. Contributions to UML and formal paradigms based on process algebras, Petri-nets, automaton theory and BDDs in the context of design, testing and formal verification techniques for integrated circuits and systems are also encouraged.

About IASTED and DTVCS 2008

The International Association of Science and Technology for Development - IASTED (http://www.iasted.org) is a non-profit organization devoted to promoting economic and cultural advancement. Established in 1977, IASTED organizes multidisciplinary conferences for academics and professionals, mainly in the fields of engineering, science, and education. IASTED holds conferences and courses in both industrialized and developing nations. Details about DTVCS can be found at: http://digilander.libero.it/systemcfl/dtvcs